1. Field of the Invention
The invention relates to a loop filter, and more particular to a loop filter capable of reducing an undesired loop current generated by offset voltage of OP amplifier in the loop filter so as to reduce the ripple of the control voltage of voltage controlled oscillator (VCO) by adjusting a compensating current of the OP amplifier in the loop filter.
2. Description of the Related Art
A phase locked loop (hereinafter referred to as PLL) is employed to generate an oscillated clock having the same phase with a reference clock. As shown in FIG. 1, a typical PLL includes a phase detector 11, a charge pump 12, a loop filter 13, a voltage control oscillator (hereinafter referred to as VCO) 14, and a frequency divider 15. The phase detector 11 detects the phase difference between an input signal IN and a phase-locked clock PLCK2, and outputs control pulses UP and DN to control the charge pump 12 according to the phase difference. Foe example, when the phase of the phase-locked clock PLCK2 leads the phase of the input signal IN, the width of the control pulse UP is smaller than the width of the control pulse DN, so that the charge pump 12 generates a negative control current Icp. The loop filter 13 reduces the control voltage Vctl according to the negative control current Icp, and thus the VCO 14 reduces the frequency of the phase-locked clock PLCK1. On the contrary, when the phase of the phase-locked clock PLCK2 lags behind the phase of the input signal IN, the width of the control pulse UP is greater than the width of the control pulse DN, so that the charge pump 12 generates a positive control current Icp. The loop filter 13 increases the control voltage Vctl according to the negative control current Icp, and thus the VCO 14 increases the frequency of the phase-locked clock PLCK1.
FIG. 2 is a circuit of a conventional loop filter. Referring to FIG. 2, the loop filter 20 includes a charge/discharge path constituted by a resistor R1 and a capacitor C1. The control current Icp charges/discharges the capacitor C1 through the resistor R1 to enable the loop filter 20 to generate the control voltage Vctl. As shown in the drawing, the control voltage Vctl is the summation of the voltage on the resistor R1 and the voltage on the capacitor C1. However, if the desired loop bandwidth of PLL is small, the capacitor in loop filter 20 becomes extremely large as to generate a proper control voltage Vctl. However, a larger capacitor may occupy larger area, and the chip cannot be miniaturized accordingly.
FIG. 3 is a circuit of another conventional loop filter. As shown in the drawing, the loop filter 30 includes a charge/discharge path constituted by a resistor R2 and a capacitor C2, and further includes a second resistor R3 and an OP amplifier 34. If the offset between the + input terminal and − input terminal of the OP amplifier 34 is ignored, the voltage of the output terminal of the OP amplifier 34 equals to the voltage of the input terminal. Therefore, the voltage of R2*I2 should be equal to the voltage of R3*I3. Consequently, as long as the ratio of the resistance of the resistor R2 to that of the resistor R3 is properly adjusted, the current flowing into the capacitor C2 may be reduced, and the capacitance of the capacitor C2 may be reduced accordingly. For example, if R2:R3 is 9:1, then I2={fraction (1/10)}*Icp, so the capacitance of the capacitor C2 also may be reduced to one-tenth of that of the capacitor C1 in the FIG. 2. However, the actual voltages at the two input terminals of the OP amplifier of the loop filter 30 are not completely the same, thereby causing a voltage difference between the first input terminal (e.g., + input terminal) and the output terminal and causing a loop current Isw accordingly. The loop current Isw may cause the voltage of the capacitor C2 to be changed and make the control voltage Vctl unstable. In addition, in order to make the loop filter 30 of FIG. 3 equivalent to the loop filter 20 of FIG. 2, the resistance of the parallel resistors R2 and R3 has to equal to that of resistor R1. Consequently, if R2:R3 is 9:1, the resistance of the resistor R2 is about ten times of that of the resistor R1. Too large resistance may cause difficulty in design.